Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to an output data strobe signal generating circuit for generating an output data strobe signal.
The typical double data rate (DDR) semiconductor memory device generates output data in synchronization with every rising time and falling timing of a clock signal. When the output data are generated, it requires outputting an output data strobe signal in synchronization with the generation of the output data. Accordingly, a receiving apparatus can receive the output data from the DDR semiconductor memory device in response to the output data strobe signal.
In other words, the DDR semiconductor memory device is provided with an output data strobe signal generating apparatus to generate an output data strobe signal, which is toggled in synchronization with every rising time and falling timing of a clock signal, in response to a read command.
The DDR semiconductor memory device outputs an output data strobe (DQS) signal and an inverted output data strobe (DQSB) signal, which have inverse phases from each other and are respectively toggled in synchronization with every rising timing and falling timing of a clock signal. In order to stably drive an output driver (TX), a “Vox” denoting a voltage difference between an output cross point voltage of the DQS signal and the DQSB signal and a half power supply voltage (VDDQ/2) of the output driver (TX) have to satisfy a preset voltage limitation, e.g., ±100 mV, as shown in FIG. 1.
Generally, when an AC characteristic of a power supply voltage of the output driver such as VDDQ and VSSQ varies according to data patterns, a drivability to the output driver (TX) also varies. As a result, the “Vox” characteristics are affected by the data patterns. Accordingly, it requires measuring the “Vox” characteristics with respect to various data patterns.
FIG. 2 is a waveform diagram illustrating various data patterns,
Referring to FIG. 2, the data patterns include an ALL-IN data pattern, an ALL-OUT data pattern, a NO-BIT data pattern, an ABAB data pattern and a BABA data pattern.
In the ALL-IN data pattern, all of the output data (DQ) have substantially the same waveform as an output data strobe (DQS) signal. In the ALL-OUT data pattern, all of the output data (DQ) have substantially the same waveform as an inverted output data strobe (DQSB) signal. In the NO-BIT data pattern, all of the output data (DQ) are fixed to a logic low level or a logic high level. In the ABAB data pattern, even data of the output data (DQ) have substantially the same waveform as the DQS signal while odd data of the output data (DQ) have substantially the same waveform as the DQSB signal. In the BABA data pattern, odd data of the output data (DQ) have substantially the same waveform as the DQS signal while even data of the output data (DQ) have substantially the same waveform as the DQSB signal.
FIG. 3 is a timing diagram illustrating variations of the Vox characteristic with respect to the ALL-IN and ALL-OUT data patterns on the basis of the NO-BIT data pattern.
Referring to FIG. 3, in the case of the NO-BIT data pattern, an output cross point voltage of the DQS signal and the DQSB signal is positioned near to a half power supply voltage (VDDQ/2). However, in the case of the ALL-IN and ALL-OUT data patterns, the output cross point voltage of the DQS signal and the DQSB signal is away from the VDDQ/2 voltage. As a result, the Vox characteristics are deteriorated.
In particular, the Vox characteristics are severely deteriorated in the ALL-IN and ALL-OUT data patterns. Since all of the output data (DQ) have substantially the same waveform as the DQS signal in the ALL-IN data pattern, a slew of the DQS signal gets smaller and thus, rising and falling timings of the DQS signal are delayed. On the contrary, since all of the output data (DQ) have substantially the opposite waveform to the DQS signal in the ALL-OUT data pattern, a slew of the DQS signal increases and thus, the rising and falling timings of the DQS signal are advanced. Likewise, the rising and falling timings of the DQSB signal are delayed or advanced as opposed to the DQS signal. As a result, the Vox characteristics are severely deteriorated.
FIG. 4 is a timing diagram illustrating variations of the Vox characteristics with respect to the ABAB and BABA data patterns on the basis of the NO-BIT data pattern.
Referring to FIG. 4, in the case of the ABAB data pattern, the rising and falling timings of the DQS signal and the DQSB signal are delayed or advanced in the same manner as the ALL-IN data pattern. In the case of the BABA data pattern, the rising and falling timings of the DQS signal and the DQSB signal are delayed or advanced in the same manner as the ALL-OUT data pattern. That is, in both cases, the Vox characteristics are further affected by the even data of the output data (DQ).
As described above, when the conventional output driver (TX) is designed, the Vox characteristics cannot satisfy the requirements of the semiconductor memory device since the rising and falling timings of the output data (DQ) and the DQS signal vary according to the data patterns.